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SI9961A
Vishay Siliconix
12-V Voice Coil Motor Driver
FEATURES
D 1.8-A H-Bridge Output D Class B Linear Operation D Externally Programmable Gain and Bandwidth D Undervoltage Head Retract D Rail-to-Rail Output Swing D Programmable Retract Current D Single 12-V Supply D Low Standby Current D System Voltage Monitor with Fault Output
DESCRIPTION
The SI9961A is a linear actuator (voice coil motor) driver suitable for use in disk drive head positioning systems. The SI9961A contains all of the power and control circuitry necessary to drive the VCM that is typically found in 31/2-inch hard disk drives and optical disk drives. The driver is capable of delivering 1.8 A at a nominal supply of 12 V. The SI9961A provides all necessary functions including a motor current sense amplifier, a loop compensation amplifier and a power amplifier featuring four complementary MOSFETs in a H-bridge configuration. The output crossover protection ensures no cross-conducting current and true Class B operation during linear tracking. Externally programmable gain switch at the input summing junction increases the resolution and dynamic range for a given DAC. The head retract circuitry can be activated by either an undervoltage condition or an external command. An external resistor is required to set the VCM current during retract.
The SI9961A is constructed on a self-isolated BiC/DMOS power IC process. The IC is available in both standard and lead (Pb)-free, 24-pin SO packages for operation over the commercial, C suffix (0 to 70_C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
V+
8 4 5
EXT VREF
7
VREF-
12
VDD
18
FAULT VCC
Voltage Monitor 8R
VR
Q1
Q3
17
IA2-
23
- +
A2
OUTPUT A OUTPUT B
R
+ -
A4 Q2 Q4
19
VR RETRACT IRET Enable OA2
9 6 11 22
VR Retract Control - + A5
Acceleration Error R
VR GAIN SELECT
7R
10
A3
- +
1
2
24
3
13
21
15 14
16
20
RINH
RINL
RFB
ISENSE OUT
ISENSE IN+
ISENSE IN-
SA
GND
SB
Document Number: 70014 S-40845--Rev. H, 03-May-04
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SI9961A
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to Common Pin V+ Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V Pin (FAULT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Pin (Output A & B, Source A & B) . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Pin (All Others) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to V+ + 0.3 V Maximum Clamp Current Output A, Output B (Pulsed 10 ms at 10% duty cycle) . . . . . . . . . . . . "1.8 A Pin (All Others) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "20 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150_C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70_C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)a 24-Pin SOICb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.125 W Thermal Impedance (QJA)a 24-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 25 mW/_C above 25_C.
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Bridge Outputs (A4, A5)
High Level Output Voltage Low Level Output Voltage Clamp Diode Voltage Amplifier Gain Dynamic Crossover Current Slew Rate Small Signal Bandwidth (-3 dB) Input Deadband -60 SR VOH VOL VCL IOH = 1.0 A, VDD = 10.2 V, OA2= VREF "1 V IOL = -1.0 A, OA2 = VREF "1 V IF = 1.0 A, ENABLE = High Output VRANGE = VREF "2 V Measured at VDD 1 0.2 60 12 16 10 8.0 9.1 0.6 1.1 2.5 18 V/V mA V/mS MHz mV V
Limits
C Suffix 0 to 70_C
Symbol
V+ = 12 V "10% VDD = 11.6 V "10% "10%, 11 6 VCC = 5 V "10%, VREF- = GND = 0 V VREF = 5 V "5%
Minb
Typa
Maxb
Unit
A2, Loop Compensation Amplifier
Input Offset Voltage Input Bias Current Unity Gain Bandwidth Slew Rate Power Supply Rejection Ratio Open Loop Voltage Gain Output Voltage Swing SR PSRR AVOL VO RLOAD = 10 kW to VREF VREF -2 @ 10 kHz VOS IB Gain Select = High, IA2- = 5 V RLOAD = 10 kW, CLOAD = 100 pF to VREF 1 50 80 VREF +2 -8 -50 1 8 50 mV nA MHz V/ms dB V
A3, Current Sense Amplifier
Input Offset Voltage Input Impedance Small Signal Bandwidth (-3 dB) Common Mode Rejection Ratio Slew Rate Gain Input Common-Mode Voltage Range Output Voltage Swing VCM VO To GND RLOAD = 10 kW, CLOAD = 100 pF to VREF CMRR SR VOS RIN ISENSEIN+ to ISENSEIN- RLOAD = 10 kW, CLOAD = 100 pF to VREF @ 5 kHz 2 3.9 -0.3 VREF -2 4 4.1 2 VREF +2 -5 5 1 50 5 mV kW MHz dB V/ms V/V V
Supply
ICC Supply Current (Normal) IV+ IDD www.vishay.com Static, No Load , RETRACT = High g ENABLE = Low 2 5 0.01 5 13 mA
2
Document Number: 70014 S-40845--Rev. H, 03-May-04
SI9961A
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Supply
ICC Supply Current (Standby) IV+ IDD VDD Range VCC Range V+ Range VDD VCC V+ Static, No Load , RETRACT = High g ENABLE = High Normal Mode Retract Mode 10.2 2.0 4.5 10.8 5 12 0.2 0.8 11.6 0.01 0.4 1.6 13.2 14 5.5 13.2 V mA
Limits
C Suffix 0 to 70_C
Symbol
V+ = 12 V "10%, VDD = 11.6 V "10% VCC = 5 V "10%, VREF- = GND = 0 V VREF = 5 V "5%
Minb
Typa
Maxb
Unit
Gain Select Switch
RFB Switch Resistance RINH Switch Resistance RINL Switch Resistance IA2- = 5 V 108 135 810 240 300 1800 W
VREF (EXT)
Input Current External Voltage Range IREF VREF OA2 = VREF 0.15 4.75 0.40 5 0.65 5.25 mA V
Power Supply Monitor
VCC Undervoltage Threshold Hysteresis V+ Undervoltage Threshold Hysteresis VREF = 5.0 V 9.1 VREF = 5.0 V 3.82 4.12 40 9.8 100 10.6 4.42 V mV V mV
Gain Select, RETRACT, ENABLE Input
Input High Voltage Input Low Voltage Input High Current Input Low Current VIH VIL IIH IIL VIN = 5 V VIN = 0 V -1 -1 3.5 1.5 1 1 V
mA
FAULT Output
Output High Voltage Output Low Voltage Output High Sourcing Current VOH VOL IOHS IOH = -100 mA IOL = 1.6 mA VOUT = 0 V VCC -0.8 VCC -0.33 0.25 400 0.50 1100 mA V
RETRACT Current Control (RETRACT = Low, Output Current from A to B)
IRET Bias Voltage Retract Output Pull-Up Voltage Retract Output Pull-Down Current Maximum Emergency Retract Current Retract Current VDD Supply Rejection Ratio Retract Current Temperature Coefficient V(IRET) VOUT A IOUTB IOUTB (Max) VDD = 10 V, RRET = 3.74 kW VDD = 2.5 V to 14 V, IOUTA = 30 mA VDD = 10 V, VOUTB = 5 V RRET = 3.74 kW RSB = 0.5 W, TA = 25_C VDD = 2 V, VOUTB = 0.7 V RRET = < 10 W, RSB = 0.5 W, VDD = 2 V to 14 V, RRET = 3.74 kW VDD = 10 V, RRET = 3.74 kW VDD -1 22 40 3.0 -0.3 %/V %/_C 30 38 0.66 V
mA
Notes a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
Document Number: 70014 S-40845--Rev. H, 03-May-04
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SI9961A
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
24-Pin SOIC (Wide Body)
RINH RINL ISENSE OUT FAULT VCC IRET EXT VREF V+ RETRACT 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 15 14 13 Top View RFB IA2- OA2 ISENSE (IN)- SOURCE B OUTPUT B VDD (Spindle Supply) OUTPUT A GND SOURCE A GND ISENSE (IN)+
ORDERING INFORMATION
Part Number
SI9961ACY SI9961ACY-T1 SI9961ACY-T1--E3
Lead (Pb)-Free Part Number
Temperature Range
0 to 70_C
Package
SOIC-24 (Wide Body)
GAIN SELECT 10 ENABLE 11 VREF- 12
APPLICATIONS
Introduction The SI9961A Voice Coil Motor (VCM) driver integrates the active feedback and drive components of a head-positioning servo loop for high-performance hard-disk applications. The SI9961A operates from a 12-V ("10%) power supply and delivers 1 A of steady-state output current. This device is made possible by a power IC process which combines bipolar, CMOS and complimentary DMOS technologies. CMOS logic and linear components minimize power consumption, bipolar front-ends on critical amplifiers provide necessary accuracy, and complimentary (p- and n-channel) DMOS devices allow the transconductance output amplifier to operate from ground to VDD. Two user-programmable, current feedback/input voltage ratios may be digitally selected to optimize gain for both seek and track following modes, to maximize system accuracy for a given DAC resolution. An undervoltage lockout circuit monitors the V+ supply and generates a fault signal to trigger an orderly head-retract sequence at a voltage level sufficient to allow the spindle motor's back EMF-generated voltage to supply the necessary head parking energy. Head retract can also be commanded via a separate RETRACT input. VCM current during retract can be user programmed with a single external resistor. External components are limited to R/C filter components for loop compensation and the resistors that are required to program gain, retract current, and the load current sense.
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User-Programmable Gains During linear operation, the transconductance amplifiers' gains (input voltage at VIN vs. VCM current, in Figure 1) are set by external resistors R3 ! R5, RSA, and RSB and selected by gain input. After selecting a value for RSA and RSB that will yield the desired VCM current level, the High and Low feedback gain ratios may be determined by the following:
R5 R3 R5 R4 1 4 RS 1 4 RS
High Gain +
(GAIN SELECT Input = High)
Low Gain +
(GAIN SELECT Input = Low)
Where RS = RSA = RSB Input offset current may then be calculated as:
1 IOS + 4 R S RS ) RIN V ) 5 VIAS3 RIN OSA2
Where RIN = R3 or R4
Document Number: 70014 S-40845--Rev. H, 03-May-04
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SI9961A
Vishay Siliconix
Back EMF Supply 5-V Ref EXT VREF
12 V System Supply V+ 4 5V VCC 5 FAULT 8
7
VREF- 12
VDD 18 IOUT VCM
mP
Voltage Monitor 8R
VR
Q1
Q3
17 A4 Q2 Q4 OUTPUT C2 R2 A 19 OUTPUT B
23 CL RL 9 6 11 22 RRET
IA2-
- +
A2
R
+ -
VR RETRACT IRET ENABLE OA2
VR Retract Control A5
Acceleration Error R
- + 7R
VR
A3 GAIN SELECT mP RINH RINL 1 2 RFB 24 10
- +
ISENSE ISENSE ISENSE OUT IN+ IN- 3 13 21
GND A 15 14 B 16 20
R3 VIN
R4
R5 RSA RSB
FIGURE 1. SI9961A Typical Application
Head Retract A low on the RETRACT input pin turns output devices Q1 and Q4 on, and output devices Q2 and Q3 off. Maximum VCM current can be set during head retract by adding an external resistor between the IRET pin and ground. Maximum retract current may be calculated as:
IOUT + 175 x Iret + 175 x 0.66 V Rret
eliminate quiescent output current when power is applied but the head has been parked, such as a sleep mode. A sleep-mode power down sequence should be preceded by a retract signal since a power failure during this state may not provide adequate spindle-motor back EMF to permit head retraction.
Transconductance Amplifier Compensation The SI9961A features an integrated transconductance amplifier to drive the voice coil motor (VCM). To ensure proper operation, this amplifier must be compensated specifically for the VCM being driven. As a first approximation, the torque constant and inertia of the VCM may be ignored, although they will have some influence on the final results, especially if large values are involved. (See Figure 1.)
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Head retract can be initiated automatically by an undervoltage condition (either the 12-V or 5-V supplies on the SI9961A) by connecting the FAULT output to the RETRACT input. A high ENABLE input puts both driver outputs in a high-impedance state. The ENABLE function can be used to
Document Number: 70014 S-40845--Rev. H, 03-May-04
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SI9961A
Vishay Siliconix
Frequency Compensation: The VCM transconductance (in siemens) of this simplified case may be expressed in the s (Laplace) plane as:
gv +
1 Lv
A = 16 x RL/10000 CL = Lv/(Rv x RL) = 100 x 10-6/RL farads Gain Optimization: There are three things to consider when optimizing the gain (A) above. The first is servo bandwidth. The main criterion here is to avoid having the transconductance amplifier cause an undue loss of phase margin in the overall servo (mechanical + electrical + firmware) loop. The second is to avoid confirguing a bandwidth that is more than required in view of noise and stability considerations. The third is to keep the voltage output waveform overshoot to a level that will not cause cross-conduction of the output FETs. The first two problems can be considered together. Let us assume a disk drive with a spindle RPM of 4400 and with 50 servo sectors per track. The sample rate is therefore:
f s + 50 440 60 This is a sample frequency of 3667 Hz
s)
Rv Lv
Where Rv = VCM resistance in ohms LV = VCM inductance in henrys s is the Laplace operator In this case, the transconductance pole is at -Rv/Lv. It is desirable to cancel this pole in the interest of stability. To do this, a compensation amplifier is cascaded with the VCM and its driver. The transfer function of this amplifier is:
s) Hc + A
1 RL
s
CL
Where RL = Compensation amplifier feedback resistor in ohms CL = Compensation amplifier feedback capacitor in farads A = Compensation amplifier and driver voltage gain at high frequency If RL x CL is set equal to Lv/Rv, then the combined open loop transconductance in siemens becomes:
gto + s A Lv
As a rule of thumb, the open loop unity gain crossover frequency of the entire servo (mechanical + electrical + firmware) loop should be less than 1/10 of the sample frequency. In this example, the servo open loop unity gain crossover frequency would be less than 367 Hz. If we allow only a 10_ degradation in phase margin due to the transconductance amplifier, then a phase lag of 10_ at 367 Hz is acceptable. This results in a 3-dB point in the transconductance at :
f3db + 367 tan (10)
In this case, the transconductance has a single pole at the origin. If this open loop transfer is closed with a transimpedance amplifier having a gain of B ohms, the resultant closed loop transconducatance stage has the transfer function (in siemens) of:
gtc +
A Lv A
or a 3-dB point in the transconductance at 2081 Hz. The pole in the closed loop transconductance (-A * B / Lv) should then be 2081 * 2 * p = 13075. This means that A = 9.8. From the above equation for A, RL = 6.2 kW. This sets the minimum gain limit governed by the servo bandwidth requirements. The gain should not be much greater than this, since increased noise will degrade the servo response. The third problem, keeping the transconductance amplifier voltage output wave form overshoot to a level that will not cause the wrong output FETs to conduct, can be evaluated by deriving the voltage transfer function of the closed loop transconductance amplifier from input voltage to output voltage (Vin to output A and B on the reference schematic). This is :
Hto + A s)p s)x
s)
Lv
B
Where B = Current feedback transimpedence amplifier gain in ohms. The entire transconductance now contains only a single pole at -A*B/Lv. A and B are chosen to be considerably higher than the servo bandwidth, to avoid undue phase margin reduction. As a typical example, in the referenced schematic, assume that Rsa and Rsb = 0.5 W, R5= R3 = 10 kW, VCM inductance (Lv) = 1.5 mH, VCM resistance (Rv) = 15 W. Hence: Rv = 15 W Lv = 1.5 mH B = 2W
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Where
p = 1/RL x CL) or Rv/Lv Comp amplifier zero/VCM pole x = A x B/Lv closed loop pole
Document Number: 70014 S-40845--Rev. H, 03-May-04
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SI9961A
Vishay Siliconix
If a unit step voltage is applied to the above transfer function and the inverse Laplace transform is taken, the output result is:
VO + A p ) (x * p) x e*x x
t
Result: In the example for the 2081-Hz roll-off case with 31% overshoot and proper pole cancellation, the compensation values are: RL = 6.2 kW CL = 0.016 mF In the example for the 1592-Hz roll-off case with no overshoot and proper pole cancellation, the compensation values are: RL = 4.7 kW CL = 0.022 mF The linearity of the transconductance amplifier (around a center value of 500 mA/volt) is shown in Figure 2. In this case, the output current sense resistors (RSA and RSB) were "5% tolerance, 0.5 W . Any mismatch between RSA and RSB contribute directly to mismatch between the positive and negative "full-scale". Including the external resistor mismatch, the overall loop nonlinearity is approximately 1% maximum over a "250-mV input voltage range.
Where
t = time
As we can see, if x = p (i.e. if the VCM pole and compensation amplifier zero = the transconductance closed loop pole), then Vo reduces to A. In other words, a step input results in a step output without overshoot. If x < p then a step input results in an increased rise time output and no overshoot. If x > p, a step input results in a step output with an overshoot.
If this overshoot is large enough, there may be a cross-conduction condition in the output FETs.
Let us look at the above equation at t = 0 and t >> 0, expressed in terms of the open loop high frequency voltage gain, A.
VO + A VO + p B Lv At t = 0 At t uu 0
5 4 Error in Percent of Full Scale 3 2 1 0 -1 -2 -3 -4 -5 -300 -200 -100 0 VIN in mV 100 200 300 VDD = 12 V RSA = RSB = 0.5 W "5% Rm = 52 W Gm = 500 mA/V
In the example shown above, p = 10,000 and A = 9.8. This means that there is some overshoot. At t = 0, the output voltage is 9.8 V per volt of input. At some later time, it has dropped to 7.5 V per volt of input. An overshoot of 31 % is thus produced.
The maximum overshoot voltage requires careful consideration, since it constitutes a potentially catastrophic problem area. If we had decided to optimize for no overshoot, A would equal 7.5, and hence the closed loop pole (A * B / Lv) would be 10,000, which is a frequency of 1.592 kHz. This would have resulted in a phase margin degradation of 13_ at the 367-Hz frequency desired. This may or may not be acceptable. One must weigh the servo bandwidth, phase margin degradation, and maximum voltage at the VCM for each individual case.
FIGURE 2. SI9961A Transconductance End Point Non-Linearity
Document Number: 70014 S-40845--Rev. H, 03-May-04
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SI9961A
Vishay Siliconix
6.2 kW RL
0.016 mF CL 8R VDD - + A2 R - + VR A4 Cross-Over Protection IOUT
RIN VIN 10 k VR
VDD A5
VCM 1.5 mH 15 W
Gain +
VIN
VS
R5 10 kW VR A3 - + R
- +
Cross-Over Protection 7R
VS (4 x Gain)
RSA 0.5 W VR
RSB 0.5 W
FIGURE 3. Transconductance Amplifier
RL = 6.2 kW , CL = 0.016 mF -5 0
RL = 6.2 kW , CL = 0.016 mF
-8 PHASE (in degrees) 10 100 Frequency (Hz) 1000 10000
-20
GAIN (in dB)
-11
-40
-14
-17
-60
-20 1
-80 1
10
100 Frequency (Hz)
1000
10000
FIGURE 4.
FIGURE 5.
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Document Number: 70014 S-40845--Rev. H, 03-May-04
Legal Disclaimer Notice
Vishay
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000 Revision: 08-Apr-05
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